ADS5270IPFP

Product Summary

The ADS5270IPFP is a high-performance, 40MSPS, 8-channel analog-to-digital converter (ADC). Internal references are provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS (low-voltage differential signaling) outputs reduce the number of interface lines and package size. An integrated phase lock loop multiplies the incoming ADC sampling clock by a factor of 12. This 12x clock is used in the process of serializing the data output from each channel. The 12x clock is also used to generate a 1x and a 6x clock, both of which are transmitted as LVDS clock outputs. The 6x clock is denoted by the differential pair LCLKP and LCLKN, while the 1x clock is denoted by ADCLKP and ADCLKN. The applications of the ADS5270IPFP include portable ultrasound systems, tape drives, test equipment, optical networking.

Parametrics

ADS5270IPFP absolute maximum ratings: (1)Supply voltage range, AVDD: -0.3V to 3.8V; (2)Supply voltage range, LVDD: -0.3V to 3.8V; (3)Voltage Between AVSS and LVSS: -0.3V to 0.3V; (4)Voltage Between AVDD and LVDD: -0.3V to 0.3V; (5)Voltages applied to external REF Pins: -0.3V to 2.4V; (6)All LVDS data and clock outputs: -0.3V to 2.4V; (7)Analog input pins: -0.3V to 2.7V; (8)Peak total input current (all inputs): -30mA; (9)Operating free-air temperature range, TA: -40℃ to 85℃; (10)Lead temperature 1.6mm (1/16″ from case for 10s): 220℃.

Features

ADS5270IPFP features: (1)Maximum Sample Rate: 40MSPS; (2)12-Bit Resolution; (3)No Missing Codes; (4)Power Dissipation: 907mW; (5)CMOS Technology; (6)Simultaneous Sample-and-Hold; (7)70.5dB SNR at 10MHz IF; (8)Internal and External References; (9)3.3V Digital/Analog Supply; (10)Serialized LVDS Outputs; (11)Integrated Frame and Synch Patterns; (12)MSB and LSB First Modes; (13)Option to Double LVDS Clock Output Currents; (14)Pin- and Format-Compatible Family; (15)TQFP-80 PowerPAD TM Package.

Diagrams